An Educational RTL-to-GDSII Flow for a Non-Pipelined 8-bit Accumulator-Based CPU Using Open-Source Tools

Designed and implemented a complete open-source RTL-to-GDSII flow for an 8-bit accumulator-based CPU, verifying six sub-blocks individually before top-level integration, achieving zero DRC/LVS errors and clean timing closure using Yosys, OpenLane 2, and the SKY130 PDK.